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november 2010 doc id 14570 rev 6 1/30 30 TDA7493 3-watt + 3-watt dual btl class-d audio amplifier features ? 3.0 w + 3.0 w of continuous output power with r l =4 ? , thd = 10%, v cc = 5 v (filterless) ? 2.8 w + 2.8 w of continuous output power with r l =4 ? , thd = 10%, v cc = 5 v (with filter) ? single supply voltage range 3.0 v to 5.5 v ? high efficiency ( = 83%) ? four selectable, fixed gain settings of 6 db, 12 db, 15.6 db and 18 db ? differential inputs mi nimize common-mode noise ? filterless operation ? standby feature ? short-circuit protection ? thermal-overload protection ? externally synchronizable description the TDA7493 is a dual btl class-d audio amplifier, specially designed for lcd tv, lcd monitors or small speakers on cradles with single-supply operation. the filterless operation allows the external component count to be reduced. the TDA7493 is assembled in the htssop24 package. thanks to the high efficiency and to the exposed-pad-down (epd) package no separate heatsink is required. htssop24 package with exposed pad down table 1. device summary order codes operating temperature range package packaging TDA7493 0 to 70 c htssop24 (epd) tube TDA749313tr 0 to 70 c htssop24 (epd) tape and reel www.st.com
contents TDA7493 2/30 doc id 14570 rev 6 contents 1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2 gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 filterless modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 internal clock and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 differential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8.1 single-ended input application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 electrical characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 for the configuration with lc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 for the configuration without filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 heatsink provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TDA7493 list of figures doc id 14570 rev 6 3/30 list of figures figure 1. TDA7493 block diagram (only one of two channels shown) . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. input high-pass rc filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. device input structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. unipolar pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. schematic for the filterless configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. master and slave modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9. typical lc filter for 8 ? speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. typical lc filter for 4 ? speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. differential input application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. single-ended input application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. anti-pop configuration for single-ended input application . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 14. simple anti-pop configuration for single-ended input application . . . . . . . . . . . . . . . . . . . . 19 figure 15. thd vs output power at 1 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. thd vs output power at 100 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. thd vs frequency at 100 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 18. thd vs frequency at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 19. output frequency response at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 20. crosstalk vs frequency at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 21. fft (0 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 22. fft (-60 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 23. thd vs output power at 1 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 24. thd vs output power at 100 hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 25. thd vs frequency at 100 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. thd vs frequency at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. frequency response at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 28. crosstalk vs frequency at 1 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 29. fft (0 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 30. fft (-60 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 31. htssop24 epd outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
list of tables TDA7493 4/30 doc id 14570 rev 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. gain selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. resistance values for input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. master and slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. htssop24 epd dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
TDA7493 device block diagram doc id 14570 rev 6 5/30 1 device block diagram figure 1 shows the block diagram of one of the two identical channels of the TDA7493. figure 1. TDA7493 block diagram (only one of two channels shown) standby svr svcc sgnd rosc inp inn gain0 pvccn outn pgndn synclk pvccp outp pgndp gain1
pin description TDA7493 6/30 doc id 14570 rev 6 2 pin description 2.1 pin-out figure 2. pin connection (top view) innl inpl standby pvccpl outpl pgndpl pgndnl outnl pvccnl synclk rosc sgnd innr inpr svr pvccpr outpr pgndpr pgndnr outnr pvccnr gain1 gain0 svcc 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 exposed pad (gnd) the exposed pad is the device ground and must be connected appropriately
TDA7493 pin description doc id 14570 rev 6 7/30 2.2 pin list table 2. pin list number name type description 1 innl in negative differential input of left channel 2 inpl in positive differential input of left channel 3 standby in standby mode control (digital): 0: standby 1: play 4 pvccpl power power supply for positive branch in left channel 5 outpl out positive pwm output for left channel 6 pgndpl power power stage ground for left channel 7 pgndnl power power stage ground for left channel 8 outnl out negative pwm output for left channel 9 pvccnl power power supply for negative branch in left channel 10 synclk in/out clock in/out for external oscillator 11 rosc out master oscillator frequency setting pin 12 sgnd power signal ground 13 svcc power signal power supply 14 gain0 in gain setting input 1 15 gain1 in gain setting input 2 16 pvccnr power power supply for negative branch in right channel 17 outnr out negative pwm output for right channel 18 pgndnr power power stage ground for right channel 19 pgndpr power power stage ground for right channel 20 outpr out positive pwm output for right channel 21 pvccpr power power supply for positive branch in right channel 22 svr output supply voltage rejection 23 inpr in positive differential input of right channel 24 innr in negative differential input of right channel
applications circuit TDA7493 8/30 doc id 14570 rev 6 3 applications circuit figure 3. typical application circuit innl inpl standby synclk rosc sgnd innr inpr svr gain1 gain0 svcc pvccpl outpl pgndpl pgndnl outnl pvccnl pvccpr outpr pgndnr pgndpr outnr pvccnr TDA7493 jumper 5 for single-ended input jumper 6 for single-ended input
TDA7493 electrical specifications doc id 14570 rev 6 9/30 4 electrical specifications 4.1 absolute maximum ratings 4.2 thermal data 4.3 electrical characteristics refer to figure 3: typical application circuit , v cc = 5 v, r l (load) = 4 ? , r1 = 39 k ? , c4 = 100 nf, f = 1 khz, g v = 18 db, tamb = 25 c, unless otherwise specified. table 3. absolute maximum rating symbol parameter negative value positive value unit v cc dc supply on pins pvccpl, pvccpr, pvccnl, pvccnr, svcc -0.3 6 v v cc_standby standby dc supply on pins pvccpl, pvccpr, pvccnl, pvccnr, svcc -0.3 7 v vi input on pins standby, innl, inpl, innr, inpr, gain0, gain1 -0.3 6 v top operating temperature 0 70 c tstg, tj storage and junction temperature -40 150 c table 4. thermal data symbol parameter min typ max unit rth j-case thermal resistance junction to case - 2 3 c/w rth j-amb thermal resistance junction to ambient (on recommended pcb) (1) 1. fr4 with via holes, copper area 9 cm2 as explained in chapter 8 on page 28 . -37-c/w table 5. electrical characteristics symbol parameter condition min typ max unit v cc supply range - 3.0 - 5.5 v iq total quiescent current no filter, no load - 7 - ma vos output offset voltage vi = 0, gv = 6 db, no load -20 - 20 mv po output power (filterless) thd = 10% - 3.0 - w thd = 1% -2.4-w po output power (with filter) thd = 10% - 2.8 - w thd = 1% -2.2-w
electrical specifications TDA7493 10/30 doc id 14570 rev 6 pd dissipated power po = 2.8 w + 2.8 w, thd = 10% -1.1-w efficiency po = 2.8 w + 2.8 w, r l =4 ? -83-% thd total harmonic distortion r l = 4 ? , po = 0.5 w - 0.05 - % tj thermal shut-down junction temperature --150-c g v closed loop gain gain0 = low gain1 = low - 6.0 - db gain1 = high - 12.0 - gain0 = high gain1 = low - 15.6 - gain1 = high - 18.0 - gv gain matching - -1 - 1 db ct crosstalk f = 1 khz - 60 - db en total output noise a curve, gv = 18 db - 50 - v f = 22 hz to 22 khz, gv = 18 db -60-v ri input resistance differential input - 60 - k ? svrr supply voltage rejection ratio f r = 100 hz, vr = 0.5 v, c svr =1f -55-db v ovp overvoltage protection threshold --5.8-v t r , t f rising and falling time - - 10 - ns r dson power transistor on resistance high side - 0.44 - ? low side - 0.36 - f sw switching frequency internal oscillator - 315 - khz f swr output switching frequency range with internal oscillator (1) 250 - 400 khz with external oscillator (2) 250 - 400 khz i qstandby quiescent current in standby --1-a function mode standby and play standby = high play - standby = low standby digital inputs digital input thresholds high 0.7 * v cc --v low - - 0.3 * v cc v 1. f sw = 10 6 / (r osc * 64 + 840) f sync = 2 * f sw with r1 = 39 k ? and f sw in khz 2. f sw = f sync / 2 with the frequency of external oscillator table 5. electrical characteristics (continued) symbol parameter condition min typ max unit
TDA7493 applications information doc id 14570 rev 6 11/30 5 applications information 5.1 mode selection pin standby selects the operating mode, namely standby or play. z in standby mode, all the circuits are turned off and there is very low leakage current. z in play mode, the amplifiers are powered up. during the turn on/off sequence, there are four operational states: standby, pre-charge, mute and play. the pre-charge and mute states are two internal transient states to set up the normal operating condition and to reduce the speaker pop noise. note: an internal pull-down resistor on pin standby ensures that the default mode is standby. 5.2 gain setting the close loop gain is set by pins gain0 and gain1 as shown below in ta bl e 7 . the gain setting is implemented by changing the feedback resistors of the amplifiers. note: internal pull-down resistors on pins gain0 and gain1 ensure that the default gain is 6 db. table 6. mode selection logic level on pin standby mode 0 standby 1play table 7. gain selection logic level on pin gain0 logic level on pin gain1 gv (nominal) 006.0 db 0 1 12.0 db 1 0 15.6 db 1 1 18.0 db
applications information TDA7493 12/30 doc id 14570 rev 6 5.3 input resistance and capacitance the input impedance is set by an internal resistor, ri, of value 60 k ? . an input coupling capacitor (ci) is required on each input line. these two components together form a high-pass filter whose cutoff frequency is: f c = 1 / (2 * * ri * ci) figure 4. input high-pass rc filter the value of ci is chosen depending on the application and the speaker system. for a cut-off frequency less than 20 hz, the input capacitors could be 470 nf each. if a polarized capacitor is used, it is important to connect the positive side of the capacitor to the terminal with higher dc voltage. the dc voltage on the input pins is v cc / 2. figure 5. device input structure ri rf rf ri ci ci input signal + -
TDA7493 applications information doc id 14570 rev 6 13/30 5.4 filterless modulation the modulation scheme of btl is called unipolar pwm output. the differential output voltage changes between zero and +v cc or between zero and -v cc , as opposed to the traditional bipolar pwm output between +v cc and -v cc . the other advantage of this scheme effectively doubles the switching frequency of the differential output waveform. signals on outp and outn are in the same phase when the input is zero, thus the current is greatly reduced and the loss in the load is small. a tiny delay between outp and outn is introduced to avoid high transient currents which could occur if both outputs switch simultaneously. TDA7493 can be used without a filter between the pwm output and the speaker since the switching frequency of the output is beyond the audible range. the audio signal can be recovered by the inherent inductance of the speaker and natural filter of the human ear. figure 6. unipolar pwm output the filterless configuration is usable in applications where the speaker connections to the amplifier are shorter than 50 cm. in comparison to the low-pass butterworth filter configuration, the filterless configuration gives rise to higher emi. this can be reduced, if necessary, by inserting a ferrite bead filters close to the device. use a ferrite which exhibits high impedance at around 1 mhz and negligible impedance in the audio band. it is recommended to use an emi filter if the speaker cable is longer than 50 cm.
applications information TDA7493 14/30 doc id 14570 rev 6 figure 7. schematic for the filterless configuration innl inpl standby synclk rosc sgnd innr inpr svr gain1 gain0 svcc pvccpl outpl pgndpl pgndnl outnl pvccnl pvccpr outpr pgndnr pgndpr outnr pvccnr TDA7493 TDA7493 amplifier (filterless) table 8. resistance values for input configuration 8 8 (*1) r2, r3, r4 and r5 are 0- ? resistors which can be replaced by ferrite beads if emi optimization is required (*2) c14, c15, c17, and c18 are 1-nf capacitors which are needed when ferrite beads are used for emi optimization
TDA7493 applications information doc id 14570 rev 6 15/30 5.5 internal clock and external clock the clock of the class-d amplifier can be genera ted internally or it can be synchronous with the external clock. if two or more class-d amplifiers are used in the same system, it is better to have all devices working at the same frequency. this is realized by using one TDA7493 as clock master and the others as slaves. all synclk pins are connected together as shown in figure 8 . in master mode or with a single TDA7493, the output switching frequency is controlled by the resistor connected to pin rosc. the switching frequency is: f sw = 10 6 / (r osc * 64 + 840) where r osc is in k ? and f sw is in khz. in this configuration pin synclk is an output whose frequency is also determined by r osc : f synclk = 10 6 / (r osc * 32 + 420) = 2 * f sw note: r osc should be lower than 60 k ? in master mode to avoid operating in error mode. in slave mode, pin rosc can be floating to force pin synclk as input in order to accept the master clock. the switching frequency in this mode is: f sw = f synclk / 2 figure 8. master and slave modes table 9. master and slave mode mode pin rosc pin synclk master r osc < 60 k ? output slave floating input master slave rosc synclk synclk rosc output input TDA7493 TDA7493 c osc 100 nf 39 k ? r osc
applications information TDA7493 16/30 doc id 14570 rev 6 5.6 output low-pass filter to avoid emi problems, a low-pass filter can be inserted before the speaker. the cut-off frequency of the filter should be higher than 22 khz and much lower than the switching frequency. the component values of the filter vary according to the speaker impedance. a typical lc output filter for a speaker impedance of 8 ? and with a cut-off frequency of 27 khz is shown in figure 9 . figure 9. typical lc filter for 8 ? speaker a similar filter for a speaker impedance of 4 ? and also with a cut-off frequency of 27 khz is shown in figure 10 : figure 10. typical lc filter for 4 ? speaker 33 h 8 ? 0.47 f 0.10 f 0.10 f 330 pf 20 ? 33 h outp outn 0.47 f 15 h outp outn 330 pf 20 ? 15 h 0.22 f 0.22 f 4 ?
TDA7493 applications information doc id 14570 rev 6 17/30 5.7 protection function the TDA7493 has four types of protection: overvoltage (ov), undervoltage (uv), thermal (ot) and short circuit (sc): z overvoltage protection (ovp) for the supply v cc > 6 v z undervoltage protection (uvp) for the supply v cc < 3 v z thermal protection (otp) for the junction temperature tj > 155 c z short-circuit protection (scp) across the load (tested at v cc = 5.0 v). when any of the above protection becomes active, the output goes to a high-impedance state. the device remains in this state until the condition is cleared or rectified, when the circuit restarts again. 5.8 differential input the TDA7493 can be used with either differential or single-ended inputs. in either case, the device must be ac coupled to the audio source. to use the device with a differential source, co nnect the positive lead from the audio source to the inp input and the negative lead to the inn input as shown in figure 11 . the differential input stage of the amplifier minimizes the common mode noise effectively. in the differential input application: z input impedance is given by 2 * rin, z cut-off frequency of the input filter is given by f c = 1 / (2 * * cin / 2 * 2 * rin) = 1 / (2 * * cin * rin). typically, rin = 30 k ? and cin > 330 nf to get a cut-off frequency less than 20 hz. figure 11. differential input application cin cin TDA7493 input stage - + audio source outp outn inp inn rin rin rfb rfb
applications information TDA7493 18/30 doc id 14570 rev 6 5.8.1 single-ended input application to use the device with a single-ended source, one input is ac connected to ground (via a capacitor) and the other input is connected to the audio source. this is designed as a fully differential input. the input scheme is shown in figure 12 . however, to avoid the start-up pop noise, it is important to equalize, as much as possible, the charging currents in the positive and negative inputs. any imbalance in these charging currents will be amplified and resu lt in the familiar turn-on pop. figure 12. single-ended input application since the input charging currents in the circuit of figure 12 can be different it is necessary to add two resistors, r0, as shown in the circuit of figure 13 . in this way the currents in the two branches of the differential input are better ba lanced and this can lead to the elimination of the turn-on pop noise. figure 13. anti-pop configuration for single-ended input application gnd cin cin TDA7493 input stage - + audio source outp inp inn rin rin rfb rfb cin cin gnd cin cin TDA7493 input stage - + audio source outp inp inn rin rin rfb rfb r0 r0
TDA7493 applications information doc id 14570 rev 6 19/30 the disadvantages of the anti-pop configuration are given below: z the input impedance or the load of audio source is no longer 2 * rin as in the case of differential input configuration but r0. it means the load effect should be considered during the application design. at this point, bigger r0 is better because of the lower load effect. z the input signal is also equivalent to v in_actual = v in * 2 * rin * (rin + rfb + r0) / (2 * ri n * (rin + rfb + r0) + rfb * r0), not the original v in which means the actual gain is reduced. when rin = 30 k ? , rfb = 30 k ? and r0 = 20 k ? , the gain is reduced by 1 db. when rin = 30 k ? , rfb = 120 k ? and r0 = 20 k ? , the gain is reduced by 1.84 db. in this case, smaller r0 is better. if the pop noise is not critical, the anti-pop configuration can be simplified as shown in figure 14 . the suggested value of the resistor r0 is 20 k ? . figure 14. simple anti-pop configurat ion for single-ended input application gnd cin cin TDA7493 input stage - + audio source outp inp inn rin rin rfb rfb r0
electrical characterization curves TDA7493 20/30 doc id 14570 rev 6 6 electrical characterization curves 6.1 for the configuration with lc filter z test setup as given in figure 3 on page 8 z test conditions v cc = 5 v, c20 = 10 f, r l = 4 ? , lc filter 15 h, 470 nf figure 15. thd vs output power at 1 khz figure 16. thd vs output power at 100 hz figure 17. thd vs frequency at 100 mw d b r a 10 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd (%) 100m 3 200m 300m 400m 500m 700m 1 2 po (w) 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 100m 3 200m 300m 400m 500m 700m 1 2 thd (%) po (w) 20 20k 50 100 200 500 1k 2k 5k 10k 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 thd (%) frequency
TDA7493 electrical characterization curves doc id 14570 rev 6 21/30 figure 18. thd vs frequency at 1 w figure 19. output frequency response at 1 w figure 20. crosstalk vs frequency at 1 w 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 20 20k 50 100 200 500 1k 2k 5k 10k thd (%) frequency -5 +2 -4 -3 -2 -1 -0 +1 20 50k 50 100 200 500 1k 2k 5k 10k 20k ampl (db) frequency (hz) crosstalk (db) frequency (hz) -120 +0 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k 50 100 200 500 1k 2k 5k 10k t t t t tt t
electrical characterization curves TDA7493 22/30 doc id 14570 rev 6 figure 21. fft (0 db) figure 22. fft (-60 db) frequency (hz) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k fft (db) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) fft (db)
TDA7493 electrical characterization curves doc id 14570 rev 6 23/30 6.2 for the configuration without filter z test setup as given in figure 7 on page 14 z test conditions v cc = 5 v, c20 = 10 f, r l = 4 ? + 270 h, no lc filter figure 23. thd vs output power at 1 khz figure 24. thd vs output power at 100 hz figure 25. thd vs frequency at 100 mw 100m 4 200m 300m 400m 600m 800m 1 2 3 po (w) 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 thd (%) 100m 4 200m 300m 400m 600m 800m 1 2 3 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 po (w) thd (%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd (%)
electrical characterization curves TDA7493 24/30 doc id 14570 rev 6 figure 26. thd vs frequency at 1 w figure 27. frequency response at 1 w figure 28. crosstalk vs frequency at 1 w 20 20k 50 100 200 500 1k 2k 5k 10k 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 frequency (hz) thd (%) 20 50k 50 100 200 500 1k 2k 5k 10k 20k -5 +2 -4 -3 -2 -1 -0 +1 ampl (db) frequency (hz) 20 20k 50 100 200 500 1k 2k 5k 10k -140 +40 -120 -100 -80 -60 -40 -20 +0 +20 t tt t t t t crosstalk (db) frequency (hz)
TDA7493 electrical characterization curves doc id 14570 rev 6 25/30 figure 29. fft (0 db) figure 30. fft (-60 db) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k fft (db) frequency (hz) -150 +10 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 20 20k 50 100 200 500 1k 2k 5k 10k fft (db) frequency (hz)
package mechanical data TDA7493 26/30 doc id 14570 rev 6 7 package mechanical data the TDA7493 comes in a 24-pin htssop exposed-pad-down package. the outline is shown in figure 31 and the dimensions are given in ta b l e 1 0 . the package code is yo and the jedec/eiaj reference number is jedec mo-153-adt. figure 31. htssop24 epd outline
TDA7493 package mechanical data doc id 14570 rev 6 27/30 in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. table 10. htssop24 epd dimensions reference mm inch notes min typ max min typ max a--1.20--0.047- a1 - - 0.15 - - 0.006 - a2 0.80 1.00 1.05 0.031 0.039 0.041 - b 0.19 - 0.30 0.007 - 0.012 - c 0.09 - 0.20 0.004 - 0.008 - d 7.70 7.80 7.90 0.303 0.307 0.311 (1) 1. dimension d does not include mold flas h, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm (0.006 inch) per side. d1 4.80 5.00 5.2 0.189 0.197 0.205 - e 6.20 6.40 6.60 0.244 0.252 0.260 - e1 4.30 4.40 4.50 0.169 0.173 0.177 (2) 2. dimension e1 does not include interlead flash or pr otrusions. interlead flash or protrusions does not exceed 0.25mm (0.010 inch) per side. e2 3.00 3.20 3.40 0.118 0.126 0.134 - e - 0.65 - - 0.026 - - l 0.45 0.60 0.75 0.018 0.024 0.030 - l1 - 1.00 - - 0.039 - - aaa - - 0.10 - - 0.004 - k0- 80- 8degrees
heatsink provision TDA7493 28/30 doc id 14570 rev 6 8 heatsink provision with the exposed-pad packages, it is possible to use the printed circuit board as a heatsink. using a pcb copper ground area of 3 x 3 cm 2 with 16 via holes to make contact with the exposed pad, a thermal resistance of 37 c/w can be achieved. the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. the maximum estimated power dissipation for the TDA7493 is around 1.1 w. with the suggested copper area of 9 cm 2 , a maximum junction temperature increase of less than 40 c above ambient can be expected, thus giving a maximum junction temperature, tj, of approximately 90 c in consumer en vironments where 50 c is specified as the maximum ambient temperature. this provides a comfortable safety margin to the thermal protection threshold at tj = 150 c.
TDA7493 revision history doc id 14570 rev 6 29/30 9 revision history table 11. document revision history date revision changes 02-apr-2008 1 initial release. 16-sep-2008 2 updated application schematic on page 8 updated table 5: electrical characteristics on page 9 updated schematic of input structure on page 12 updated schematic for the filterless configuration on page 14 updated section 5.8: differential input on page 17 . 01-dec-2008 3 added test voltage note to sc protection in section 5.7: protection function on page 17 . 14-dec-2008 4 replaced 2.8 w with 3 w in title on page 1 added new feature of 3.0 w on on page 1 updated description for pin standby in table 2: pin list on page 7 added output power for filterless config to table 5: electrical characteristics on page 9 updated values for digital input thresholds in table 5: electrical characteristics on page 9 updated text for environmentally-friendly packaging on page 27 . 14-oct-2009 5 updated minimum operating voltage on page 1 and on page 9 updated formula for f sw on page 10 and on page 15 . 29-nov-2010 6 added v cc_standby to table 3: absolute maximum rating on page 9
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